Four layers between a design and a good chip
Each layer can undo the gains of the one before it: perfect patterning wasted by uncontrolled etch, perfect etch wasted by missed measurement.
Patterning
Masks, resists, exposure, alignment, and computational correction define intended geometry.
- Measure
- Pitch · overlay
- Failure boundary
- Stochastic defects at this scale are probabilistic, not deterministic, the same process can pass or fail a given die.
Where the frontier moves
Computational lithography and EUV that keep pushing achievable pitch down.
Materials and process
Deposition, etch, implant, anneal, and cleaning build three-dimensional devices.
- Measure
- Uniformity · selectivity
- Failure boundary
- Atomic-scale variation compounds across dozens of sequential steps.
Where the frontier moves
New materials and process chemistries that hold tolerance at ever-smaller scale.
Metrology and control
Optical, electron, X-ray, electrical, and statistical methods measure and steer the process.
- Measure
- Uncertainty · throughput
- Failure boundary
- The accuracy-speed trade-off means the most precise tools are too slow to check every wafer.
Where the frontier moves
Hybrid metrology that combines fast inline tools with periodic high-resolution calibration.
Yield and packaging
Wafer test, repair, chiplets, bonding, and final test convert patterned area into sellable systems.
- Measure
- Good dies/wafer
- Failure boundary
- Compound yield across every prior stage determines the die's real cost, not its nominal node.
Where the frontier moves
Chiplet architectures and redundancy that tolerate defects instead of requiring perfection.
Atomic dimensions turn averages into distributions
At small dimensions, a few atoms, photons, or molecules can change a feature. Manufacturing must bound variation and uncertainty rather than assume a perfectly repeatable line.
Why does die size drive cost faster than geometry alone?
The model uses the standard gross-dies-per-wafer geometry formula and Murphy's yield model, the two textbook building blocks of semiconductor cost accounting.
591 good dies from 640 gross dies per wafer
- Die yield (Murphy model)
- 92.4%
- Gross dies per wafer
- 640
- Good dies per wafer
- 591
Public reporting on TSMC's 3-nanometer node cites wafer prices near $20,000 and defect densities around 0.09–0.14 defects/cm² in early-to-mature production. At those inputs, a 600 mm² die lands near 50% yield, consistent with industry commentary that large leading-edge dies often yield only 40–50% good chips.
Calculation and boundaries
Gross dies per wafer ≈ (π × (diameter/2)² ÷ die area) − (π × diameter ÷ √(2 × die area)), the standard geometric approximation accounting for edge loss. Murphy yield = ((1 − e^(−D₀×A)) ÷ (D₀×A))², where D₀ is defect density and A is die area in cm². Cost per good die = wafer cost ÷ good dies. Excludes design cost, mask cost, packaging, test, and yield ramp over time, a mature-node figure, not a first-silicon figure.
Scaling moves from geometry into control
As structures become vertical and heterogeneous, edge placement, interfaces, strain, composition, thermal behavior, and package alignment create a multidimensional process window.
Hybrid metrology
Combine fast indirect inline measurement with slow, high-resolution calibration tools.
Computational correction
Model masks, exposure, etch, and equipment drift to correct for known process variation.
Design for yield
Use redundancy, chiplets, and tolerant layouts that survive a realistic defect rate.
Learn faster
Turn inline data into process adjustments before wafers are lost, not after a batch fails test.
Who is building what
High-NA EUV lithography, gate-all-around nanosheets, backside power delivery, and cryogenic etch determine yield at atomic dimensions. Search the record, or filter by fab layer.
ASMLTwinscan EXE:5000 & 5200 (High-NA EUV)0.55 Numerical Aperture (High-NA) extreme ultraviolet lithography with anamorphic optics providing 8nm resolution in a single exposure
- Reported evidence
- Shipped first EXE:5000 tools to Intel Oregon and imec joint lab; demonstrated 10nm line printing without multi-patterning.
- Announced next step
- Full commercial volume manufacturing insertion on 2nm and sub-2nm foundry nodes.
- Unresolved risk
- Half-field size (anamorphic magnification) requiring field stitching for large dies, and tool purchase prices exceeding $350M each.
TSMCN2 & A16 NodesNanosheet GAAFET (Gate-All-Around) architecture transitioning to A16 with Super PowerRail backside power delivery network (BSPDN)
- Reported evidence
- Pilot production underway at Fab 20 in Hsinchu; demonstrated superior threshold voltage uniformity and gate control over FinFETs.
- Announced next step
- High-volume N2 mass production in 2025, followed by A16 commercial deployment in 2026.
- Unresolved risk
- Defect density in multi-layer nanosheet release etches and thermal dissipation bottlenecks with backside metal routing.
Intel FoundryIntel 18A NodeRibbonFET GAA architecture combined with PowerVia backside power delivery, using standard 0.33 NA EUV with advanced multi-patterning
- Reported evidence
- Tape-out and power-on of lead customer chips (Panther Lake and Clearwater Forest); demonstrated functional compute silicon.
- Announced next step
- Regaining process leadership and offering merchant foundry services to external hyperscale customers.
- Unresolved risk
- Wafer yield ramp across full die areas, cost of EUV double-patterning, and competing for external foundry customer commitments.
Samsung FoundryMBCFET 3nm / 2nmMulti-Bridge-Channel FET (MBCFET) nanosheet GAA architecture with customizable nanosheet channel widths
- Reported evidence
- First foundry to announce commercial 3nm GAA shipment in 2022; second-generation 3nm and 2nm process optimization underway.
- Announced next step
- Scaling high-performance mobile and AI accelerator wafer production with competitive defect densities.
- Unresolved risk
- Early commercial yield challenges on complex high-area logic dies and customer qualification timelines.
Applied MaterialsCentris Sym3 & Centura SculptaPattern-shaping etch tools (Sculpta) that stretch features in one direction to eliminate EUV exposures, paired with atomic-layer deposition (ALD)
- Reported evidence
- Commercial tool deployments in leading logic and memory fabs; demonstrated reduction in required EUV lithography mask passes.
- Announced next step
- Widespread adoption across sub-2nm nodes to cut lithography cost and wafer defect probability.
- Unresolved risk
- Feature edge roughness control and pattern placement errors during extreme directional plasma etching.
KLA CorporationBroadband Plasma & e-Beam InspectionDeep ultraviolet broadband optical inspection and multi-beam electron review systems identifying sub-optical defects across full 300mm wafers
- Reported evidence
- Dominant market share in wafer defect inspection and metrology across all tier-1 advanced logic and DRAM fabs.
- Announced next step
- High-throughput metrology capable of detecting buried voids in backside vias and multi-tier nanosheets.
- Unresolved risk
- Throughput limitations of fine e-beam inspection scanning billions of contacts per square centimeter.
Lam ResearchCryogenic Dielectric EtchSub-zero wafer chuck temperatures (-60°C to -80°C) enabling ultra-high aspect ratio dielectric etching with minimal chemical taper
- Reported evidence
- Production deployment in 3D NAND manufacturing (up to 300+ layers) and advanced packaging TSV (through-silicon via) fabrication.
- Announced next step
- Transitioning cryogenic etch into advanced logic nanosheet release and backside power via drilling.
- Unresolved risk
- Chamber cooling thermal cycle times and managing complex fluorocarbon condensation on wafer surfaces.
imecHigh-NA EUV Joint Lab & Sub-1nm ScalingPre-competitive research consortium uniting ASML, tool makers, and foundries to benchmark resists, pellicles, and CFET (Complementary FET) architectures
- Reported evidence
- Demonstrated operational High-NA EUV imaging and pioneered 3D stacked CFET prototypes stacking nMOS directly on pMOS.
- Announced next step
- Roadmaps extending silicon CMOS down to the A5 (0.5nm equivalent) node into the 2030s.
- Unresolved risk
- Materials limits (metal resistivity skyrocketing at sub-10nm line widths) and economic feasibility of $20B+ fab constructions.
Node names (e.g., '2nm', '18A') are marketing designators, not physical gate lengths or half-pitches. Transistor density, defect density, and wafer yield govern real economics.
The optimistic view, with conditions
The nanometer becomes a systems capability
Future gains will come from co-optimizing device architecture, process, measurement, design, and packaging rather than shrinking a single printed dimension.
Computational correction keeps extending the curve
Modeling equipment drift and exposure lets fabs hold tolerance without a purely optical breakthrough.
Design absorbs defects it cannot prevent
Chiplets and redundancy convert a fixed defect density into a smaller effective yield loss.
The die stops being the whole product
Advanced packaging turns yield economics into a system-level, not single-die, optimization.
What industrial-yield nanometer manufacturing actually needs
- Metrology that keeps paceMeasurement precise and fast enough to steer the process it is meant to control.
- Realistic defect accountingYield modeled honestly against die area, not assumed away by a node name.
- Design for yieldRedundancy and chiplet architectures that tolerate a real-world defect rate.
- Fast feedback loopsInline data turned into process correction before wafers are lost, not after.
- System-level optimizationPackaging and architecture co-designed with the process, not bolted on after.
The fab is now part of the product cost
The Semiconductor Industry Association’s 2026 testimony puts a leading-edge fab at roughly $20–25 billion including construction and tools; it describes more than 1,000 production steps and individual equipment prices from about $5 million to over $300 million. This is an industry estimate of capital at the leading edge, not an average cost for every chip. More transistors per wafer only lower cost per transistor when yield, throughput and utilization offset that capital.
TSMC reported $40.9 billion of consolidated capital expenditure in 2025. Packaging is a separate scale-up layer: NIST announced $1.4 billion of finalized advanced-packaging awards in January 2025, which are funding commitments, not qualified manufacturing output. A true node cost curve needs yield-adjusted good dies and delivered system performance at a fixed design and volume; nominal node names and transistor density alone cannot show whether the cost curve still falls.
Design cost and yield now move together
The Semiconductor Industry Association estimates design cost at about $30 million for a 65 nm chip in 2006 and more than $540 million for a 5 nm chip in 2020. Those are estimated complete-design budgets, not wafer prices or a universal per-transistor cost curve. TSMC reports N2 entered high-volume manufacturing in late 2025, with N2P and A16 volume production targeted for the second half of 2026; “good yield” in its annual report is a company statement without a public monthly defect-density curve.
Imec's 2025 High-NA EUV experiment measured electrical yield on 20 nm pitch metal lines, showing why stochastic pattern defects and interconnects matter alongside transistor density. A foundry node label is a marketing family, not a 2 nm silicon feature. A comparable cost-per-working-transistor series would need wafer price, usable die area, actual transistor count, yield and package cost on the same product class; most of those are confidential.
Sources, method, and boundaries
Measurement claims come from NIST programs. The cost equation is an accounting identity; no node-to-node commercial cost claim is inferred without fab-specific yield data. The interactive model applies textbook gross-dies-per-wafer geometry and Murphy's yield formula to publicly reported wafer-price and defect-density ranges, an illustration of the mechanism, not an audited cost for any named product or foundry.
- D₀ (defect density)
- The average number of yield-limiting defects per unit wafer area for a given process.
- Murphy yield model
- A standard formula estimating die yield that accounts for defect clustering, more realistic than simple Poisson yield for most processes.
- Overlay error
- Misalignment between two patterned layers on a chip, which can break electrical connections if too large.
